Electronic Design Process Symposium

Parallel Computing: Can We PLEASE Do it right this time?

Tim Mattson

Intel

Embedded Boot Camp: AMP vs. SMP

Grant Martin

Steve Leibson @Tensilica

Max Out Your Multi's (An Embedded Perspective)

Radhika Thekkath

MIPS

Myths of Multicore

Ian Rickards

ARM

Processor Centric Designs Are Dead

Ray Brinks

Sonics Inc.

Parallel Computing Bingo

Patrick Madden

SUNY

Th Future of EDA Standards [Panel Organizer]

John Darringer

IBM

EDA Standards: The Spirit View

Gary Delp

SPIRIT

Creating Effective EDA Standards

Jake Buurma

Steven Schultz @ SI2

IP Challenges, and potential opportunities: A Global Standards POV

Victor Berman

Improv Systems

IEEE Standards: Focus on Test Technology

Rohit Kapur

Synopsy

The Electrical Design-Manufacturing Interface

Puneet Gupta

UCLA

Blaze

Regular Designs and Computational Lithography: Their Past, Present, and Future

Andres Torres

Mentor Graphics

After the Hype, Are We Ready To Do DFM? [Author Bio]

Anantha Sethuraman

DFMSim

Tuning EDA flows (using TCL)

Patrick Groeneveld

Magma

Efficient Use of Multicore Processors for Timing Analysis

Joao Geada

CLKda

On Libraries, Reuse, and the Value of EDA Software

Igor Markov

U Michigan

Synplicity

An Updated Venture Capital Outlook

Juan-Antonio Carballo

Argon VC

Multi-Voltage Power Managment Verification Issues

Bhanu Kapoor

Auturo Salz @ Synopsys, Shankar Hemmady @Mimasic

Multicore Design: OpenSPARC T1 and T2

Aman Joshi

Sun Microsystems

Multicore Embedded Software Development on Virtual Platforms

Larry Lapides

Imperas

Virtualization for software developers

Michel Genard

Virtutech

Parallel Atomic Transactions + Parameterization: the breakthrough for SoC Design

Rishiyur Nikil

Bluespec

FinSimMath: An Extension of Verilog for Mathematical Descriptions

Alec Stanculescu

Fintronic

EDP Banquet Dinner Discussion on EDA and the Industry Press

Richard Goering

SCDsource

Gabe Moretti @ GabeOnEDA, Steve Leibson @ EDN

Semiconductor Trends and Investments

Renu Raman

Tallwood VC

Solutions for SoC Design

Akash Deshpande

ARC

The Forecast for EDA

Daya Nadamuni

Gary Smith EDA

The Next EDP Challenge: Cost of ASIC Design & Validation

Rajesh Gupta

UC San Diego

Verification Minimization with Karnaugh Maps

Srivasta Vasudevan

Synopsys