Electronic Design Process Symposium

Welcome to IEEE/DATC EDP 2007!

Bhanu Kapoor

Atrenta

slides (in PDF)

Design Rules: From Restriction to Prescription

Leon Stok

IBM

slides (in PDF)

Words of Power: Reusable, Holistic, Scalable Multi-voltage Design

Herve Menager

NXP

slides (in PDF)
... and also paper (in PDF)

SoCs for Portable Video Applications: Architecture level Considerations

Mahesh Mehendale

Texas Intruments

paper (in PDF)

Blurring the Layers of Abstractions: Time to take a step back?

Krisztian Flautner

ARM

slides (in PDF)

Wireless Low Power Design and Verification Challenges

Milind Paddhye

Freescale

slides (in PDF)
... and also paper (in PDF)

EDA to the Rescue of the Silicon Roadmap

Marco Casale-Rossi

Synopsys

slides (in PDF)

Should Power Management Govern Design Hierarchy?

Ed Huizbregts

Magma

slides (in PDF)

Power Management Early in the Design Flow: Exploration to Implementation

Holly Stump

Sequence Design

slides (in PDF)

Fitting DFM in your design flow: It's all about Cost

Michael Smayling

Tela Innovations

paper (in PDF)
... and also slides (in PDF)

DFM: The path toward maturity through innovation and consistent added value

Sorin Dobre

QualComm

slides (in PDF)

Fitting DFM in your design flow

Rajesh Raina

Freescale

paper (in PDF)
... and also slides (in PDF)

Analysis is from Venus, Synthesis from Mars: Scenes from a DFY marriage

Patrick Groeneveld

Magma

slides (in PDF)

Hardware Acceleration for DFM/RET: 'Accelerating Design For Manufacturing (DFM) and the Electronic Design Process (EDP) using the Cell BE Microprocessor Architecture'

Frank Schellenberg

and

Nick Cobb, Dragos Dudau, Raghu Chalisani, James McKibbin, Steve McPherson @ Mentor, Mercury Systems

paper (in PDF)
... and also slides (in PDF)

Standard Setting at Si2: A Synergistic, End-User Driven Approach

Sumit DasGupta

Si2

slides (in PDF)
... and also paper (in PDF)

EDA Standards: The Way I See It

Karen Bartleson

Synopsys

slides (in PowerPoint format (.ppt))

An Efficient Method for Leakage Optimization in Timing Critical Designs

Shrikrishna Pundoor

and

R. Venkatraman @ Texas Instruments

paper (in PDF)

40 Years of Amdahl's Law

Patrick Madden

SUNY

A 180 GFLOP/s, 15 GFLOP/W 500 million transistor FPGA in 90nm CMOS

Ashok Vittal

and

H. K. Verma @ Velogix

An Automated Core Power Network Closure Methodology

Jairam S.

TI India

and

Venkatraman R., Jeff Rudolph, Udaykumar H., Jagdish Rao

Concurrent Programming Crisis

Daya Nadamuni

DFM Market Perspective

Gary Smith

Gary Smith EDA

Getting Power Management to Work

Srikanth Jadcherla

Archpro Design Automation

Latency and Throughput are Dead

JoAnn Paul

Virginia Tech

Low-Power: Today's Hot Topic

Dennis Brophy

Mentor

Multi-core ESL [Dinner Talk]

Grant Martin

Tensilica

Multiprocessor Architectures: Software Programming Challenges and Solutions

Frank Schirrmeister

Imperas

New Data Exchange Standards Without New Parsers

Igor Markov

U. Michigan

New Wave of Design Technology Venture Capital: the Global Start-up

Juan-Antonio Carballo

Argon

Process Variation Tolerant Circuit Design

Kaushik Roy

Purdue

So Many Cores, So Little Time

Andrew Singer

Rapport

Technology Roadmap for DFM

Andrew Kahng

UC San Diego