Electronic Design Process Symposium

Scaling Methodology

Dan Smith

Nvidia

slides (in PDF)

The Future of High-Level Modeling and System-Level Design: Some Scenarios

Grant Martin

Cadence Design Systems

paper (in PDF)
... and also slides (in PDF)

Bridging the High-level and Implementation Divide: Mission Impossible?

Victor Konrad

Intel

paper (in PDF)
... and also slides (in PDF)

SystemC abstractions and design refinement for HW-SW SoC designs

Dundar Dumlugol

CoWare/SystemC

slides (in PDF)

SpecC Methodology for High Level Modeling

Rainer Doemer

UCI/SpecC

paper (in PDF)
... and also slides (in PDF)

A Methodology for SoC Top-Level Validation using Esterel Studio

Lionel Blanc

Esterel Technologies

and

Amar Bouali, Jerome Dormoy, Olivier Meunier

paper (in PDF)
... and also slides (in PDF)

Breaking Down Complexity for Reliable System-Level Timing Validation

Dirk Ziegenbein

Technical University of Braunschweig

and

Marek Jersaks, Kai Richter, Rolf Ernst

paper (in PDF)
... and also slides (in PDF)

TACO: Rapid Design Space Exploration for Protocol Processors

Seppo Virtanen

Turku Centre for Computer Science

and

Johan Lilius, Tero Nurmi, Tomi Westerlund

paper (in PDF)
... and also slides (in PDF)

Platform-based Design: Report from the Front

Daniel Martin

Infineon Technology

and

Sagheer Ahmad, Kambiz Khalilian

paper (in PDF)
... and also slides (in PDF)

Platform-Based Design and the First Generation Dilemma

Jiang Xu

Princeton

and

Wayne Wolf

paper (in PDF)
... and also slides (in PDF)

Platform-based Co-Design and Co-Development: Experience, Methodology and Trends

Grant Martin

Cadence Design Systems

and

Jean-Yves Brunel

paper (in PDF)
... and also slides (in PDF)

Evolving ASIC Methodology to Adapt to Technology and EDA Tool Advances [Invited]

Tom Russell

IBM

slides (in PDF)

Managing Risk in Block Based Designs: A Front End Acceptance Methodology

Kumar Venkatramani

Cadence

and

Stefanus Mantik

paper (in PDF)
... and also slides (in PDF)

Policy-Based RTL Design

Bhanu Kapoor

Atrenta

and

Bernard Murphy

paper (in PDF)
... and also slides (in PDF)

Providing Physical Vision to RTL Designers

Shankar Krishnamoorthy

Synopsys

slides (in PDF)

Noise in the RTL Signoff Flow

Vivek Joshi

Intel

slides (in PDF)

Engagement Model Dependent Sign-off

Dan Deisz

LSI Logic

slides (in PDF)

Collaboration Methodologies and Best Practices for IP Development and SOC Design

Dennis Harmon

Synchronicity

paper (in PDF)

A New Methodology for Analog/Mixed-Signal (AMS) SoC Design that Enables AMS Design Reuse and Achieves Full-Custom Performance

Kazuhiro ODA

Toshiba

and

Lou Prado @NeoLinear, Anthony J. Gadient

paper (in PDF)
... and also slides (in PDF)

Synthesizable full custom mixed signal IP

Mar Hershenson

Barcelona Design

and

Dave Colleran

slides (in PDF)

A Revolutionary New Solution to Unified RF Systems and Circuit Design

James Spoto

Applied Wave Research

paper (in PDF)
... and also slides (in PDF)

Cost Savings through Reuse

Aparna Dey

Synchronicity

paper (in PDF)
... and also slides (in PDF)

IP Authoring and Integration for HW/SW Co-Design and Reuse - Lessons Learned

Frank Schirrmeister

Cadence Design Systems

and

Martin Meindl, Stan Krolikoski

paper (in PDF)
... and also slides (in PDF)

Reuse and Quality Enhancement via Computation and Distribution of Component Derivative Rewards

Juan-Antonio Carballo

IBM

and

Wendy Belluomini, Robert Montoye, David Cohn

paper (in PDF)
... and also slides (in PDF)

Design Tool Advances Drive ASIC Signoff Paradigm Shift

Tom Russell

IBM

Evolution of Sign-off Models

Tommy Eng

Tera Systems