Our Cast
Majid Ahadi
Keysight Technologies
Majid Ahadi Dolatsara received the B.Sc. degree in electrical engineering from K. N. Toosi University of Technology, Tehran, Iran, in 2013, the M.Sc. degree in electrical engineering from Colorado State University, Fort Collins, CO, USA, in 2016, and the Ph.D. degree in electrical and computer engineering from Georgia Institute of Technology, Atlanta, GA, USA, in 2021. He has won the Richard B. Schulz best paper award in transactions on electromagnetic compatibility in 2022. He is currently employed by Keysight Technologies, Calabasas, CA, USA, as a research and development software engineer, working on electronic design automation software. His research interests include development of numerical and machine learning algorithms for high performance simulation in the field of signal and power integrity, and high-speed channel simulation.
Rob Aslett
Si2
Rob is the President and Chief Executive Officer of Silicon Integration Initiative Inc. (Si2) where he is responsible for elevating the profile and impact of Si2 to be an indispensable partner for improving efficiencies through IC design flow integration and standards development in the semiconductor industry. Rob has over 30 years of experience leading global technical organizations and has held multiple leadership roles in strategy, research, development and support of electronic design automation (EDA) software, methods and flows for designing and validating integrated circuits. Rob is an investor partner with Social Venture Partners of Portland, a leader in applying venture philanthropy to create social impact. Rob is also an occasional guest lecturer at Portland State University's graduate class for Engineering and Technology Management, which utilizes the book he co-authored with John M. Acken and Siva K Yerramilli titled, "A Perspective on Holistic Engineering Management" (Foreward by Pat Gelsinger).
Jyotika Athavale
Synopsys
Jyotika is a Director and Principal Architect at Synopsys, leading Silicon health and Lifecycle Management RAS architecture for automotive and data center use cases. Prior to Synopsys, she was Lead Technologist, Functional Safety Architecture at NVIDIA, driving capability development, safety architectures and methodologies, system safety engineering activities and pathfinding for safety critical systems. Prior to NVIDIA, Jyotika was Principal Engineer (Director) at Intel Corporation where she led corporate-wide RAS and Functional Safety methodologies and architectures for automotive, data center and avionics use cases.
Jyotika also serves as the 2024 President of the worldwide IEEE Computer Society, overseeing overall IEEE-CS programs and operations. She chairs the IEEE P2851 Standard on Functional Safety interoperability which has WG membership from over 30 companies. For her leadership in service, Jyotika was awarded the IEEE Computer Society Golden Core Award in 2022. She was also recognized as a Distinguished Alumna by her alma-mater VJTI. Jyotika has a Master's Degree in Electrical Engineering from Iowa State University. She has authored patents and many technical publications in various international conferences and journals.
Norman Chang
Semiconductor BU, ANSYS
Norman Chang co-founded Apache Design Solutions in February 2001 and currently serves as Ansys Fellow and Chief Technologist of Electronics, Semiconductor, and Optics BU, ANSYS, Inc. He is also currently leading AI/ML and security initiatives at ANSYS. Prior to Apache, he lead a research group on Power/Signal/Thermal Integrity of chipsets based on VLIW architecture at HP Labs. Dr. Chang received his Ph.D. in Electrical Engineering and Computer Sciences from University of California, Berkeley. He holds 25 patents and has co-authored over 60 IEEE papers and a popular book on "Interconnect Analysis and Synthesis" by Wiley-Interscience at 2000. He is in the committee of EDPS, ESDA-EDA and SI2 AI/ML SIG, and an IEEE Fellow
Chris Cheng
Hewlett-Packard Enterprise
Chris Cheng is a Distinguished Technologist at the Storage Division of Hewlett-Packard Enterprise. He is responsible for managing all high speed, analog and mixed signal designs within the Storage Division. He also held senior engineering positions in Sun Microsystems where he developed the original GTL system bus with Bill Gunning. He was a Principal Engineer in Intel where he led high speed processor bus design team. He was the first hardware engineer in 3PAR and guided their high-speed design effort until it was acquired by Hewlett Packard.
Debendra Das Sharma
Intel
Dr. Debendra Das Sharma is an Intel Senior Fellow and co-GM of Memory and I/O Technologies in the Data Platforms and Artificial Intelligence Group at Intel Corporation. He is a leading expert on I/O subsystem and interface architecture.
Dr. Das Sharma is a member of the Board of Directors for the PCI Special Interest Group (PCI-SIG) and a lead contributor to PCIe specifications since its inception. He is a co-inventor and founding member of the CXL consortium and co-leads the CXL Board Technical Task Force. He co-invented the chiplet interconnect standard UCIe and is the chair of the UCIe consortium.
Dr. Das Sharma has a bachelor's in technology (with honors) degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur and a Ph.D. in Computer Engineering from the University of Massachusetts, Amherst. He holds 175 US patents and 450+ patents world-wide. He is a frequent keynote speaker, plenary speaker, distinguished lecturer, invited speaker, and panelist at the IEEE Hot Interconnects, IEEE Cool Chips, IEEE 3DIC, SNIA SDC, PCI-SIG Developers Conference, CXL consortium, Open Server Summit, Open Fabrics Alliance, Flash Memory Summit, Intel Innovation, various Universities (CMU, Texas A&M, Georgia Tech, UIUC, UC Irvine), and Intel Developer Forum. He has been awarded the Distinguished Alumnus Award from Indian Institute of Technology, Kharagpur in 2019, the IEEE Region 6 Outstanding Engineer Award in 2021, the first PCI-SIG Lifetime Contribution Award in 2022, and the IEEE Circuits and Systems Industrial Pioneer Award in 2022.
Harish Dixit
Meta
Harish Dixit is a Principal Engineer (Release to Production) at Meta. Harish and team work on reliability, analytics and performance evaluation for all of deployed fleet of servers.
Harish leads the efforts to deal with silent data corruptions within Meta infrastructure across CPUs, GPUs and ASICs, and has been working across different layers of the stack to mitigate the effects of silent data corruption on production applications. Harish has over 20 patent filings across system architecture and communication domains. As part of this talk, Meta will be giving an overview of silent data corruptions, their prevalence in large scale infrastructure with a case study, and efforts to mitigate them at scale.
These efforts are also published
as "Silent Data Corruptions at Scale"
and "Detecting silent data corruptions in the wild" for the curious reader.
Shankar Hemmady
Blue Horizons
Shankar Hemmady is the founder of Blue Horizons, a San Francisco based company focused on the last-mile problem of Generative AI based solutions in two enterprise markets. Their team has significant expertise in Generative AI, AI-ML, Blockchain, 5G-6G, Cloud and Edge computing, 3D-IC, RISC-V, Cybersecurity and Functional Safety. Over the past 25 years, Shankar conceived, invested in, marketed and delivered several new products primarily in three verticals: electronic design automation, biotechnology and education. Most of them involved applying new hardware and software paradigms, especially AI.
Chia-Tung Ho
Nvidia Research
Chia-Tung Ho is a research scientist in the Design Automation research group at Nvidia Research. He received the B.S. and M.S. degrees in electrical engineering and computer science from National Chiao Tung University, Hsinchu, Taiwan, in 2011 and 2013, respectively, and the Ph.D. degree in electrical and computer engineering from the University of California San Diego, USA, in 2022. Chia-Tung has several years of industrial EDA experience under his belt. Before coming to US, he worked for IDM and EDA companies in Taiwan, developing in-house design for manufacturing (DFM) flow at Macronix, and fastSPICE at Mentor Graphics and Synopsys. During his PhD study, he worked with the Design Technology Co-Optimization (DTCO) team in Synopsys as a technical intern from 2019 to 2021, also as an AI resident in X, the Google moonshot factory for 9 months. His research interests include reinforcement learning for circuit design, generative model for EDA optimization, machine learning for VLSI design, and DTCO pathfinding.
Martin Keim
Siemens
Dr. Martin Keim joined the Tessent product group of Mentor Graphics in 2001, now part of Siemens Digital Industries Software, where he is Senior Engineering Director responsible for the Memory Testing, Built-In Self-Test Diagnosis products, IJTAG infrastructure, as well as Multi-die testing.
For several years, Dr. Keim has worked on the organizing committee of the International Symposium for Testing and Failure Analysis (ISTFA), for which he was General Chair in 2016. He is past member of the IEEE 1687-2014 working group, and General Chair of the current IEEE P1687 Refresh working group.
He holds several national and international patents and is author of numerous technical publications. He received a doctorate in Informatics from the Albert-Ludwigs University in Freiburg im Breisgau, Germany.
Shiva Kintali
True Dat
Dr. Shiva Kintali is a Mathematician, Cryptographer, Theoretical Computer Scientist and a Game-Theorist. His research interests include AI Safety, Explainable AI and Privacy-preserving Federated Machine Learning. He received his PhD from GeorgiaTech, Masters from USC and B-Tech from IIT Kharagpur. He taught at Princeton University for four years
Bharat Krishna
Ampere Computing
Bharat Krishna is a Vice President of information Technology at Ampere Computing. He is responsible for the High-Performance Computing infrastructure and services required to design the most complex cloud-native microprocessors for data centers. Prior to that, Bharat was with Intel Corporation since 1995 when he joined the company as a CAD engineer. Starting with the Pentium MMX project and continuing to the most recent Xeon products, Bharat has contributed to many microprocessor projects that were key to the world's digitization.
In his career, Bharat has held many engineering and management roles including, Physical Design Manager, Design Automation Director, Post-Silicon Electrical Validation. He is leveraging his experience in design automation to drive innovation in IT services for EDA workloads.
Bharat is an established Digital Transformation leader focusing on the optimization of large-scale operations He is passionate about automation and creating systems that enable users to be more productive.
Bharat received a Ph.D. degree in Computer Engineering from Syracuse University in 2005.
Sung Kyu Lim
Georgia Tech
Prof. Sung Kyu Lim received Ph.D. degree from UCLA in 2000. He joined the School of Electrical and Computer Engineering at the Georgia Institute of Technology in 2001, where he is currently Motorola Solutions Foundation Professor. His research focuses on the architecture, design, and electronic design automation for 2D, 2.5D, and 3D ICs using conventional and AI algorithms. He has published more than 400 papers on the topics. He received the Best Paper Award from the IEEE Transactions on CAD in 2022 and the ACM Design Automation Conference in 2023. He began serving as a program manager for DARPA Microsystems Technology Office (MTO) since 2022 to create and manage programs in 3D IC design automation. He is an IEEE fellow.
David Pan
UT Austin
David Pan (Fellow of ACM, IEEE, and SPIE) is a Full Professor and holder of Silicon Laboratories Endowed Chair at the Chandra Department of Electrical and Computer Engineering, The University of Texas at Austin. His research interests include electronic design automation, synergistic AI and IC co-optimizations, design for manufacturing, hardware security, and design/CAD for analog/mixed-signal and emerging technologies. He has published over 480 refereed journal/conference papers and 9 US patents. He has served in many editorial boards and conference committees, including various leadership roles such as DAC 2024 Program Chair, DAC 2023 Program Co-Chair, ICCAD 2019 General Chair, and ISPD 2008 General Chair. He has received many awards, including 20 Best Paper Awards (from TCAD, DAC, ICCAD, DATE, ASP-DAC, ISPD, HOST, SRC, IBM, etc.), SRC Technical Excellence Award, DAC Top 10 Author Award in Fifth Decade, ASP-DAC Frequently Cited Author Award, NSF CAREER Award, IBM Faculty Award (4 times), and many international CAD contest awards. He has held various advisory, consulting, or visiting positions in academia and industry, such as MIT and Google. He has graduated 52 PhD students and postdocs who have won many awards, including ACM Student Research Competition Grand Finals 1st Place (twice, 2018 and 2021), and Outstanding PhD Dissertation Awards 5 times from ACM/SIGDA and EDAA.
Partha Saha
Wipro
Partha has completed a Master's Degree with First-class Distinction in Data Science and Engineering from Birla Institute of Technology and Science, Pilani (BITS Pilani). Partha has 10 years of Industrial work experience & Currently working as an AI Lead Data Scientist at Wipro. He is a Google's Udacity Bertelsmann Technology scholar, got accepted into New York University (NYU) for the AI Summer School'22 program, and was awarded ICML'21 and CLPsych for ACL 2022 as a student volunteer. His research interests are Natural Language Processing, Conversational AI, Deep learning, and Text Mining.
Warren Savage
Applied Research Laboratory for Intelligence and Security at U. of Maryland
Warren Savage is currently a Visiting Researcher at the University of Maryland's Applied Research Laboratory for Intelligence and Security, primarily supporting DARPA programs as a subject matter expert on a variety of research programs. He is perhaps one of the most recognized figures in Silicon Valley having held various technical and executive roles in semiconductor, EDA, and systems companies including Fairchild, Tandem Computers, and Synopsys where he made an impact on a then nascent semiconductor intellectual property industry. He went on to found IPextreme in 2004, a semiconductor IP commercialization company, which was sold to Silvaco in 2016. Mr. Savage holds four patents, a BS in Computer Engineering from Santa Clara University and an MBA from Pepperdine University
Naresh Sehgal
Deeply Human AI
Naresh K. Sehgal recently worked at NovaSignal Corp for 3 years as the Sr. VP of Cloud Engineering and CISO (Chief Information Security Officer). Before that, he was at Intel for more than 31 years in various engineering and management roles. Naresh has earned a B.E. (Electrical Engineering) from Punjab Engineering College, M.S. and Ph.D. from Syracuse University in Computer Engineering. Naresh has taught Cloud Computing at Santa Clara University and earned an MBA.
Dongkai Shangguan
Thermal Engineering Associates
Dr. Dongkai Shangguan, IEEE Fellow & IMAPS Fellow, is President of Thermal Engineering Associates Inc. (TEA), and a Strategic Advisor to innovative companies in the global semiconductor and electronics industry. Previously, he served as Corporate Vice President at Flex (formerly Flextronics) and as Chief Marketing Officer at STATSChipPAC (currently JCET). Early in his career, he held various technical and management responsibilities at Ford Electronics and Visteon.
Dr. Shangguan has published two books, authored/co-authored over 200 technical papers, and has been issued 31 U.S. patents.
Dr. Shangguan has served on the iNEMI Board of Directors, the IEEE EPS Board of Governors, and the IPC Board of Directors. He is currently an IEEE EPS Distinguished Lecturer. He has received a number of recognitions for his contributions to the industry, including the Electronics Manufacturing Technology Award and the Outstanding Sustained Technical Contribution Award from IEEE EPS, the William D. Ashman Achievement Award from IMAPS, the President's Award from IPC, and the Total Excellence in Electronics Manufacturing Award from the Society of Manufacturing Engineers.
Dr. Shangguan received his B.Sc. degree in Mechanical Engineering from Tsinghua University, China, MBA degree from San Jose State University, and Ph.D. in Materials from the University of Oxford, U.K. He conducted post-doctoral research at the University of Cambridge and The University of Alabama.
Tameesh Suri
Applied Materials
Tameesh Suri is an Engineering Director within Applied AI Solutions (AIS)/Applied AI where he leads performance efforts on heterogenous integration (HI) and chiplet-based architectures. His focus areas span a broad range of architectural aspects to establish comprehensive PPA trade-off analysis and projections for HI. This includes developing detailed frameworks to measure and analyze impact of AI, GPU and CPU workloads on disaggregation - specifically, scalability of CPU/SoC/Accelerator architectures and the memory subsystem. He has significant breadth and depth of experience in Server SoCs/DL accelerator architectures and worked on many industry-leading products. Prior to joining Applied Materials, Tameesh worked at Cerebras Systems, Intel Corporation and Samsung Semiconductors. He holds a PhD in EE from State University of New York at Binghamton and has published his work in several IEEE/ACM conferences and journals. He has 10+ US patents (issued and pending).
Lav Varshney
U of Ill
Lav Varshney is an associate professor of electrical and computer engineering at the University of Illinois Urbana-Champaign, and co-founder of Kocree, Inc., a startup company using novel human-integrated AI in social music co-creativity platforms to enhance human collaboration and wellbeing across society. He is a former White House staffer, having just served on the National Security Council staff as a White House Fellow, where he contributed to national AI and wireless communications policy. Previously at IBM Research, he led the development and deployment of the Chef Watson system for culinary creativity as the first commercially successful generative AI technology that also received worldwide acclaim. At Salesforce Research, he was part of the team that open-source released the largest and most capable large language model at the time. His work and public scholarship has been featured in media ranging from Fox News and the Wall Street Journal to the New York Times, NPR, Slate, and The New Yorker. He has appeared in the Robert Downey, Jr. documentary series, Age of AI. He holds a B.S. degree in electrical and computer engineering from Cornell University and S.M. and Ph.D. degrees in electrical engineering and computer science from the Massachusetts Institute of Technology.
Zhibin Xiao
Moffett AI
Dr. Zhibin Xiao has over a decade of hardware-software co-design experience in developing CPU, DSP and hardware accelerators including video codec, database and machine learning. Currently, Dr. Xiao is the co-founder and Chief Architect of Moffett AI, where he leads the development of Sparse AI Accelerators and Systems for data-center applications. Previously, Dr. Xiao was a founding team member of Alibaba cloud chip business unit and worked in AI chip and ARM CPU projects as a chip architect. Before Alibaba, he worked in Oracle as Principal Engineer in the Software in-Silicon Team, building several generations of in-memory database accelerator (DAX) inside SPARC CPU chip. Dr. Xiao has published 17+ papers and holds 15+ US patents. He received his BS and MS degrees from Zhejiang University in 2003 and 2006, respectively and earned his PhD degree in Computer Engineering from University of California, Davis in 2012.
Yervant Zorian
Synopsys
Dr. Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. He is President of IEEE Test Technology Technical Council (TTTC), the Founder of IEEE 1500 Standardization Working Group, and General Chair of the 50th Design Automation Conference (DAC) and 50th International Test Conference (ITC). He authored 5 books, 400 referred papers, and holds 45 US patents. A Fellow of IEEE, Dr. Zorian has been the recipient of 2005 IEEE CAS Industrial Pioneer Award, 2006 IEEE Hans Karlsson Award, 2014 Republic of Armenia's National Medal of Science, and 2022 IEEE TTTC Lifetime Contribution Medal.