Our Cast
Pushkar Apte
SEMI
Dr. Apte serves as Strategic Technology Advisor and leads the Global Data & Artificial Intelligence (AI) Initiative at SEMI, the electronics industry consortium representing 3300+ companies worldwide. His work focuses on two exciting opportunities at the intersection of semiconductors and AI – innovative, system-level solutions to accelerate innovation in AI, and digital twins to improve efficiency of semiconductor research & development, design and manufacturing.
Dr. Apte received his Master's and Ph.D. degrees from Stanford University in Materials Science and Electrical Engineering, and his Bachelor's degree in Ceramic Engineering from the Indian Institute of Technology, Varanasi, India. Dr. Apte also holds an Executive M.B.A. from Southern Methodist University.
Until June 2024, Dr. Apte served as Director of Strategic Initiatives at the University of California, Berkeley, where he built industry-academic partnerships to create intelligent technology solutions for challenging business and societal applications. Previously, Dr. Apte has worked with Texas Instruments Incorporated on cutting-edge research and technology development for semiconductors, with McKinsey & Company as their Global Semiconductor Business Expert, and with the Semiconductor Industry Association as Vice President of Technology. Dr. Apte has served on the Executive Boards of the Semiconductor Research Corporation, International SEMATECH, and the International Technology Roadmap for Semiconductors.
Dr. Apte has over 50 publications and presentations in prestigious international journals, conferences, and institutions, including several Invited Papers. He has received the Norman Hackerman Young Author Award from the Electrochemical Society for Best Paper in the Journal of the Electrochemical Society, and the Graduate Student Award from the Materials Research Society for Outstanding Research Performance. Dr. Apte also holds 2 U.S. Patents.
Sathishkumar Balasubramanian
Siemens
Sathish currently leads the product management and marketing organization for CustomIC Verification (CICV) division at Siemens. Sathish is an experienced product leader with over 20+ years of experience in EDA industry. Sathish's focus is on bringing value to semiconductor ecosystem through innovative solutions. Sathish is proficient in scaling product portfolio growth and expansion of market share/revenue through relentless focus on data-based execution and thought leadership.
Prior to Siemens, Sathish held various product management, strategic business development and corporate development roles for Cadence Design Systems and Synopsys. Sathish received his BS in Electronics & Communication from University of Madras, MS in computer engineering from University of Alabama & MBA from UC Berkeley- Hass School of Business.
Sreejit Chakravarty
Ampere Computing
Dr. Sreejit Chakravarty is an IEEE Fellow, a highly recognized Researcher, Inventor, and a Distinguished Engineering Leader, with extensive industry and academic experience.
He is currently a Distinguished Engineer at Ampere Computing, Santa Clara, CA, USA where he drives the strategic initiatives for product quality. Prior to this he had over 25 years of industry experience as a Principal Engineer with Intel Corporation and Distinguished Engineer at LSI and AVAGO (now Broadcom). He started his career in academia as an Associate professor of Computer Science, at The State University of New York at Buffalo, where his work was funded by multiple National Science Foundation Grants.
He has architected innovative solutions across the entire silicon life cycle spanning Silicon Quality and Reliability (RAS, Functional Safety and Silent Data Errors); and subsequently drove them from concept to product intercept.
He has published 1 book, authored 145+ IEEE papers and has 23 issued US patents. He has served in various capacity at numerous IEEE conferences and delivered multiple keynote addresses, the latest being at the IEEE Asina Test Symposium, 2023. He has mentored research at several universities like Princeton, USC, UIUC, etc. For his professional work he has been recognized as an IEEE Fellow and SUNY Distinguished Alumni. He currently chairs the IEEE P3405 Work Group on Chip-let Interconnect Test and Repair, which aims to standardize the test and repair of chip-let interconnects which will lay the foundation to realize the chip-let revolution.
Norman Chang
Electronics, Semiconductor, and Optics BU, Ansys
Norman Chang co-founded Apache Design Solutions in February 2001 and currently serves as Ansys Fellow and Chief Technologist at Electronics, Semiconductor, and Optics BU, ANSYS, Inc. He is also currently leading AI/ML and security initiatives at ANSYS. Prior to Apache, he lead a research group on Power/Signal/Thermal Integrity of chipsets based on VLIW architecture at HP Labs. Dr. Chang received his Ph.D. in Electrical Engineering and Computer Sciences from University of California, Berkeley. He holds 31 patents and has co-authored over 60 IEEE papers and a popular book on ”Interconnect Analysis and Synthesis” by Wiley-Interscience at 2000. Dr. Chang is an IEEE Fellow for his contribution on ”Leadership and contributions to the physical-level sign-off of Electronic Design Automation for SoC/3DIC”. He is also a recipient of 2024 ”Distinguished Entrepreneur of the Year” Award from Chinese Institute of Engineers (CIE). He also actively engages in industry committees such as IEEE EDPS (Electronic Design Process Symposium) and SI2
Chris Cheng
Hewlett-Packard Enterprise
Distinguished Technologist, Electrical
Pradeep Dubey
Intel
Pradeep K. Dubey is an Intel Senior Fellow and director of the Parallel Computing Lab, a part of the Intel Labs organization at Intel Corporation. He leads a team of top researchers focused on state-of-the-art research in parallel computing. Dubey and his team are responsible for defining computer architectures that can efficiently handle emerging machine learning/artificial intelligence, traditional HPC applications for data-centric computing environments, and deriving product differentiation opportunities for Intel's CPU and GPU processing platforms. Dubey previously worked at IBM's T.J. Watson Research Center. Dubey has made significant contributions to the design, architecture and application performance of various microprocessors, including the IBM Power PC, the Intel386™, Intel486™, Intel® Pentium®, and Intel Xeon® processors. He holds 36 patents and has published more than 100 peer-reviewed technical papers. In 2012, Dubey was honored with an Intel Achievement Award for breakthroughs in parallel computing research, and was honored with Outstanding Electrical and Computer Engineer Award from Purdue University in 2014. Dubey holds a Ph.D. in electrical engineering from Purdue University. He is a Fellow of IEEE and also an ACM Fellow.
Paul Harrison
Cadence
Paul Harrison is a Senior Principal Application Engineer at Cadence Design Systems. He is in the engineering team that generates, delivers, and supports CFD-based data center digital twins for clients.
He studied at the University of Sheffield in the UK to obtain his masters in Mechanical Engineering and has been working at Future Facilities (FF) and then Cadence Design Systems, following its acquisition of FF in 2022, for the past 13 years.
He has many years experience of data center optimization protects using CFD. He also enjoys research and development to find innovative ways to improve the Reality DC platform. His achievements have been recognized by the data center industry through winning two awards.
Gopal Hegde
SiMa.ai
Gopal Hegde heads engineering & operations at SiMa.ai. A veteran of multiple silicon valley startups and large companies, Gopal joined SiMa.ai in 2020 and over the last 4 years built a strong engineering & operations team that has successfully delivered multiple silicon, software and platform products while supporting dozens of customers across multiple embedded edge verticals. Gopal joined SiMa.ai from Marvell Semiconductors where he was the VP/GM of server processor business. He joined Marvell through Marvell's acquisition of Cavium Inc. Prior to Cavium, Gopal was part of executive teams at Calxeda, Cisco Systems (where he was responsible for development and delivery of Cisco's Unified Computing Systems (UCS) platforms), Intel, Level One and Digi International. Gopal has an MSECE from University of Massachusetts Amherst and ME in Computer Science and Engineering from Indian Institute of Science, Bengaluru.
Vishal Khandewal
Synopsys
Vishal is a Chief Architect in the EDA Group at Synopsys leading the Fusion Compiler physical optimization team. He has extensive R&D experience in state-of-the-art Place&Route engines and flows, including applying machine-learning techniques to improve PPA and runtime.
Vishal has a Ph.D. from University of Maryland and has authored over 30 patents and IEEE/ACM publications, including best paper winners at DAC-2023, ISPD-2021 and ISPD-2007.
Shiva Kintali
R3AI
Dr. Shiva Kintali is the Founder & CEO of R3AI. He is a Mathematician, AI researcher, Cryptographer, Theoretical Computer Scientist and a Game-Theorist. His research interests include AI Safety, Explainable AI and Privacy-preserving Federated Machine Learning and Cryptography. He received his PhD from GeorgiaTech, Masters from USC and B-Tech from IIT Kharagpur. He taught at Princeton University for four years.
Akhilesh Kumar
Ansys
Akhilesh Kumar is a Senior Principal R&D Engineer at Ansys leading the AI/ML and Generative AI solutions for the Semiconductor BU products. He has deep experience in developing advanced EDA reliability solutions such as substrate noise analysis, ESD and electrothermal/thermal analysis, including developing AI/ML EDA solutions. Akhilesh received his PhD in Electrical and Computer Engineering from the University of Waterloo. He has over 20 publications in major journals and conferences, more than 10 US patents and applications and won the 2022 Ansys CEO innovation award. He is also the co-chair of the Si2 AI/ML SIG and received the 2023 Si2 Pinnacle Award for his contributions to advancing the AI/ML in EDA.
Ala Moradian
Applied Materials
Ala Moradian is a director at the Computational Product and Solutions (CPS) Center of Excellence at Applied Materials where he is focused on epitaxy technology and digital twins for semiconductor manufacturing.
Over more than a decade at Applied, Ala has worked on different products and business units such as ion implant, rapid-thermal processing, epitaxy, physics-based simulation and led the development of several new technologies and products.
His roles included CFD expert, heat transfer subject matter expert, scientist/physicist, program lead and product manager.
He is also the intellectual property technologist for Epitaxy business unit at Applied Materials.
Ala obtained his PhD in mechanical engineering from University of Toronto, a master's from Sharif University of technology, and a Masters in management from Harvard University.
Ala is a Fellow of American Society of Mechanical Engineers (ASME), and an adjunct faculty at UC Berkeley. He has over 20 publications and over 70 US patents and applications.
Ronjon Nag
Stanford Medicine
Dr. Ronjon Nag, Adjunct Professor, Stanford Medicine; President R42 Group. Ronjon Nag has been building AI systems for 40 years and co-founded or advised companies sold to Motorola, RIM/BlackBerry, and Apple.
He is a venture capitalist with his firm R42, which invests in AI and longevity companies.
He became a Stanford Interdisciplinary Distinguished Careers Institute Fellow in 2016.
He teaches AI, genes, and ethics courses at Stanford Medicine.
He received a PhD from Cambridge, an MS from MIT, the IET Mountbatten Medal, the $1 million Verizon Powerful Answers Award, and the 2021 IEEE-SCV Outstanding Engineer Award.
Dr. Nag is the 2024 inductee into the Silicon Valley Engineering Hall of Fame. He is part owner of some 100 AI and biotech startups.
Chandrakant Patel
HP
Chandrakant is a Senior Fellow at HP Inc. He leads HP's global technical community and the company's technology strategy. He has delivered innovations in chips, systems, data centers, storage, networking, print engines and software platforms. Chandrakant is a pioneer in thermal and energy management in data centers, and in application of the information technology to drive available energy management at city scales. His current technical interests are focused on sustainable cyber-physical systems built on domain fundamentals, machine generated data and AI.
Chandrakant is a Fellow of the American Society of Mechanical Engineers (ASME) and a Fellow of Institute of Electrical and Electronics Engineers (IEEE), holds 164 patents, and has published more than 150 technical papers. An advocate of the return to fundamentals, he has served as an adjunct faculty in engineering at Chabot College, U.C. Berkeley Extension, San Jose State University and Santa Clara University. In 2014, Chandrakant was inducted into the Silicon Valley Engineering Hall of Fame. In 2018, he was inducted into the United States National Academy of Engineering (NAE).
Mark Ren
NVidia
Haoxing (Mark) Ren is the Director of Design Automation Research at NVIDIA, focusing on leveraging machine learning and GPU-accelerated tools to enhance chip design quality and productivity.
He has over 20 years of industrial EDA research experience at IBM Research and NVIDIA Research.
He holds over twenty patents and has co-authored over 100 papers and books, including a book on ML for EDA and several book chapters in EDA.
He received several prestigious awards for his work, including the IBM Corporate Award and best paper awards at ISPD, DAC, TCAD, MLCAD, and LAD.
He earned his Ph.D. from the University of Texas at Austin and is a Fellow of the IEEE.
Naresh Sehgal
Deeply Human AI
Naresh K. Sehgal is currently the CTO at Deeply Human AI, Inc.
Before that he worked at NovaSignal for 3 years and at Intel for 31 years in various Engineering and Management roles. Naresh has earned his B.E. from Punjab Engineering College, M.S. and Ph.D. from Syracuse University.
He taught a Cloud Computing class at Santa Clara University and earned an MBA. Naresh has 7 patents, co-authored 5 books, and published 40 technical papers in various conferences and journals
Ashkan Seyedi
NVidia
Ashkan Seyedi received a dual bachelor's in electrical and computer engineering from the University of Missouri-Columbia and a Ph.D. from University of Southern California working on photonic crystal devices, high-speed nanowire photodetectors, efficient white LEDs, and solar cells. With a decade of industry experience at Intel, Hewlett Packard Enterprise and now NVidia, Dr. Seyedi has been working on developing high-bandwidth, efficient optical interconnects for exascale, and high-performance computing applications.
Qian Wang
U. Cal. Merced
Qian Wang is currently a faculty member at the Electrical Engineering department of University of California, Merced. Before joining the academic realm, she worked at Intel as a research scientist. Her expertise lies in hardware security, particularly in investigating the security properties of SoC systems. At Intel, she focused on designing and validating cryptography algorithms embedded within chips, ensuring robust security measures. Her research interests lie at the crossroads of hardware security and machine/deep learning with a focus on practical applications in domains such as autonomous vehicles, anomaly detection, hardware/circuit security, and cryptographic circuitry.
Jianjun Xu
Keysight
Dr. Jianjun Xu is recognized internationally as a leading innovator of advanced artificial neural network (ANN) technology and its practical applications to a wide range of microwave and RF engineering problems. He is presently Senior Machine Learning Engineer at Keysight Laboratories, Keysight Technology, Inc., in Santa Rosa CA.
His ANN research has been integrated into leading commercial simulators and measurement-based design flows, including transistor characterization and nonlinear modeling of GaAs and GaN FETs, cryogenic CMOS devices, lithium-ion battery models, TCAD-to-circuit links, and more.
Dr. Xu received the Ph.D. Degree in Electrical Engineering from Carleton University, Ottawa, Canada, in 2004, and is a frequent technical reviewer for the IEEE on topics of AI/ML and ANNs.