Talks with Archived Presentations
Tradeoffs in bulk planar FET, FD-SOI, and FinFET Design
Tom Dillinger
Oracle
slides (in PDF)
3D IC EcoSystem Today and What's Next
Herb Reiter
EDA 2 ASIC
slides (in PDF)
3D-IC Designs for Power, Performance, and Cost
Brandon Wang
Cadence
slides (in PDF)
Verification and Extraction of 3D Stack Component Interactions
Dusan Petranovic
Mentor
slides (in PDF)
Hybrid Pre-SI Platforms for Accelerated Software Development
Vikramjeet Singh
NVIDIA
slides (in PDF)
Hybrid Virtual Platforms: Are They the Highbred of Virtual Platforms?
Vinoo Srinivasan
Intel
slides (in PDF)
Stop Abstracting! Use the Real Design Earlier for Software Verification Using Hybrid Approaches
Frank Schirrmeister
Cadence
slides (in PDF)
The Need for Speed: 'Hybrid-emulation'
Russell Klein
Mentor Graphics
slides (in PDF)
A Journey Through History from Mainframes to Smartphones
Dileep Bhandarkar
IEEE Life Fellow
slides (in PDF)
Power: What’s the problem?Industry trends and solutions in low power design
Steve Carlson
Cadence
slides (in PDF)
Power Aware Architecture Design for Multicore SoCs
Pat Sheridan
Synopsys
slides (in PDF)
A Roadmap for Low-Power Design: Trends, Technology, Tools
Andrew Kahng
UCSD
slides (in PDF)
Talks Delivered, but without Archived Presentations
FinFET vs FD-SOI
Kelvin Low
Samsung SSI
FinFET vs FD-SOI
Boris Murmann
Stanford University
FinFET vs FD-SOI
Marco Brambilla
Synapse Design
2015 EDPS Program Committee
General Chair: Aparna Dey @ Cadence
- Naresh Sehgal @ Intel
- Gary Smith @ Gary Smith EDA
- John Swan @ Intel
- Herb Reiter @ EDA 2 ASIC
- Daniel Nenni @ SemiWiki
- Gene Matter @ Docea Power
- Dwight Hill @ Synopsys
- Camille Kokozaki @ NetApp
- Steve Grout @ Consultant
