Talks with Archived Presentations
Going Beyond Shift Left: Platform Acceleration with Pre-Silicon Prototyping Solutions
Chris LawLess
Intel
slides (in PDF)
Combining TLM & RTL Techniques:A Silver Bullet for Pre-Silicon HW/SW Integration
Frank Schirrmeister
Cadence
slides (in PDF)
An Approach to Verification of Many-Core Systems Using the Virtual Platform
Vicki Mitchell
Altera
slides (in PDF)
Top Semiconductor Design Flow Challenges System Level Integration
Frank Schirrmeister
Cadence
slides (in PDF)
Top 10 Reasons Internal IP Reuse Fails... and What YOU Can Do About It
Warren Savage
IPextreme
slides (in PDF)
2014 EDPS Program Committee
- John Swan @ Swan on Chips
- Camille Kokozaki @ NetApp
- Naresh Sehgal @ Intel
- Dwight Hill @ Synopsys
- Gary Smith @ Gary Smith EDA
- Herb Reiter @ EDA 2 ASIC
- Daniel Nenni @ SemiWiki
- Steve Grout @ Consultant
General Chair: Aparna Dey @ Cadence