Abstract for panel discussion on parallel EDA. Electronic Design Process Symposium, 2001.

Speaker: Juan Rey, Mentor Graphics

The computational demands of IC designs grow with each process node. At the same time, the trend in computer hardware is towards use of multiple cores. To maintain the required design schedules and time to market, it is imperative for EDA applications to scale efficiently on general multi-core platforms. The challenges of parallel EDA are numerous, but fall into two broad buckets:

1) Algorithmic invention, which tends to be proprietary with slow progress,

2) Practical engineering concerns which have proprietary elements but are a natural area for collaboration, and include:

i) The need for a cooperative/competitive framework (use as example SRC:  look at two “nodes down”) for pre-competitive research challenges

ii) The need for training and a qualified candidate pool

iii) The need for early access to computer/compiler/OS releases.

This presentation will outline the many core reality using CPU vendor roadmaps to illustrate the trends. It will then describe the challenges faced by the EDA industry in developing parallel applications as outlined above. It will be a call for how to find commonality of pre-competitive EDA problems and how to pose them to the academic community.