Electronic Design Process Symposium

Do We Need Robust Tools?

Igor Markov

U. Michigan

High-Level Design: (Yet) Another Look

Rajesh Gupta

UC San Diego

Challenges and Opportunities of ESL Design Methodology

Deming Chen

U of Illinois [joint]

Data Management Challenges of CPU Design

Kiron Pai

Intel

Doing MORE with less [Keynote]

David Stanasolovich

Intel

High Performance Computing for Silicon Design

Shesha Krishnapura

Intel

Dealing with Hard Serial Bottlenecks

Patrick Madden

SUNY

Parallel Computing and the RTL to GDS Flow

Tom Spyrou

Cadence

EDA and Cloud Computing

James Colgan

Xuropa

Where is the EDA Research Going? How to Run an EDA Contest?

Cliff Sze

IBM

EDA = Electronics Design Automation: Are You Kidding?

Andreas Kuehlmann

Cadence

Conceptual Framework of Side Channel Attack Resistant Secure CAD Flow

Biswabeep Chatterjee

Intel

Power Management: A System Perspective

Stephen Olsen

Low Power & Impact On Verification

Prapanna Tiwari

Synopsys

Design Flows for Optimal Power Designs

Carl Sechen

U Texas

Mechanical Computing Redux: Relays for IC Applications

Tsu-Jae King

UC Berkeley

MEMs for RF

Cong Khieu

Cavendish Kinetics

3D Circuit Design with Through-Silicon-Via:Challenges and Opportunities

Sung Kyu Lim

GTCAD Laboratory

3D IC's

Rahul Deokar

Parallel EDA

Patrick Groeneveld