Authors: Ram Sunder, Pradeep Buddharaju, Khalil Siddiqui, Santhosh Pillai, Madhavi Tagare and Robert Farmer.

The paper describes the methodologies for a successful design of complex system-on-a-chip (SOC) solutions, in a sub-micron process. The key issues, CAD tools and methodologies, will be discussed and

Solutions for quick turnaround and consistent quality will be presented.

The design of the solution, integrating these components, impacts both the system architecture and the system costs. The primary objectives of these simplified solutions are cost and simplicity, at the system level. Reduction of die size and power are critical to the success of the program.

Achievement of these goals is complicated by the need to have very short design cycles and frequent feature changes to the definition of the product.

The numerous components, that comprise the system-on-a-chip solution, have different specifications. Entirely different definition groups such as DTS, Dolby Laboratories, MPEG, Macrovision in addition to the customer drive the specifications. The integrated solution is driven as much by the definition of the components as by the ability of the design team to spin variants, which capture the latest specifications.

Hierarchy definition has been critical for managing design size and complexity. In such SOC solutions, hierarchy is critical to manage the schedule of the project, by reducing the impact of the last component on the assembly of the integrated solution. It also allows the integration team the means to spin versions of one or more components without having to spin the entire SOC design another time.

The challenges and solutions, to address issues on layout floorplans, pad rings, power distribution, isolation of power, clock distribution and signal planning, will be discussed. The current state of the commercial CAD tools will be discussed and the challenges that lie ahead for automation.

The challenges of working in the sub-micron process (0.25um and 0.18 um) with the requirement for very short design cycles, are many. It is critical to note that most CAD tools available are focussed on analysis and identification of problems AFTER the design is completed. While this step is important, it has a major impact on the product cycle. The oft-used term, correct-by-design, is an achievable goal with the application of the correct methodology. Developing such methodologies is the key to a recipe that enables a design team to duplicate its success. For example, signal reliability is a critical issue. The methodologies, to address this problem at the synthesis phase of the cycle, will be discussed.

The methodology and tool flow should be carefully designed such that integration of CAD software from different vendors is simplified. Investment in large design automation teams, for the purpose of tool integrations and training of the design team, is beyond the reach of most IC design teams. This paper will discuss the CAD tools used at Mediamatics, the interfaces between the tools and use of industry-standard formats such PDEF and SDF to minimize the use of "glue" software to make the different tools work together.

Ram Sunder: Director, National Semiconductor, responsible for physical design activities at the Mediamatics division.

Pradeep Buddharaju, Khalil Siddiqui, Santhosh Pillai, Madhavi Tagare and Robert Farmer are members of his team.